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Freescale Semiconductor /MKM14ZA5 /SIM /SCGC5

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Interpret as SCGC5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SLCD 0 (0)PORTA 0 (0)PORTB 0 (0)PORTC 0 (0)PORTD 0 (0)PORTE 0 (0)PORTF 0 (0)PORTG 0 (0)PORTH 0 (0)PORTI 0 (0)IRTC 0 (0)IRTCREGFILE 0 (0)WDOG 0 (0)XBAR 0 (0)TMR0 0 (0)TMR1 0 (0)TMR2 0 (0)TMR3

TMR3=0, PORTI=0, PORTE=0, WDOG=0, PORTD=0, XBAR=0, PORTF=0, PORTA=0, SLCD=0, PORTC=0, IRTC=0, PORTH=0, PORTB=0, TMR2=0, PORTG=0, TMR0=0, IRTCREGFILE=0, TMR1=0

Description

System Clock Gating Control Register 5

Fields

SLCD

Segmented LCD Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTA

PCTLA Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTB

PCTLB Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTC

PCTLC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTD

PCTLD Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTE

PCTLE Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTF

PCTLF Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTG

PCTLG Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTH

PCTLH Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTI

PCTLI Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
IRTC

IRTC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
IRTCREGFILE

IRTC_REG_FILE Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
WDOG

Watchdog Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
XBAR

Peripheral Crossbar Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
TMR0

Quadtimer0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
TMR1

Quadtimer1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
TMR2

Quadtimer2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
TMR3

Quadtimer3 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data